The invention relates to a line error checking circuit for an electric data transmission system having a first line and a second line for differentially transmitting binary data pulses in such a manner that a first logic value of the data pulses has a high potential on the first line and a low potential on the second line associated therewith, and a second logic value of the data pulses has a low potential on the first line and a high potential on the second line associated therewith.
A data transmission system usually includes a larger number of data locations that are interconnected by means of two lines and of which at least one is capable of operating both as transmitter and as receiver.
A first advantage of such differential transmission via two lines consists in that interference pulses reaching both lines in equal manner are eliminated in the differential assessment of decoding of the data pulses transmitted via the lines. A second advantage consists in that such a differentially operating data transmission system displays redundancy with respect to a number of line errors, so that error-free transmission thus is still possible if the two lines are shorted to each other if one of the two lines is open or if one of the two lines is shorted to a ground potential or a supply potential.
More detailed explanations in this respect can be found in DE 195 23 031 A1.
Such a differentially operating data transmission system can be a CAN system. The term CAN stands for Controller Area Network. Closer details in this respect can be found in the book xe2x80x9cController Area Network: CANxe2x80x9d by Konrad Etschberger, Carl Hanser Publishing House 1994, ISBN No. 3-446-17596-2.
Such CAN systems are employed for example in the field of motor vehicles.
It is known from said DE 195 23 031 A1 to use three comparators in receiving locations of such a differentially operating data transmission system for decoding the transmitted data pulses, with a first one of said comparators comparing the potentials on the two lines with each other, a second one comparing the potential of the first line with a mean potential between low potential and high potential of the data transmission system, and a third one comparing the potential of the second line with the mean potential. The output signals of the three comparators are supplied to an error recognition circuit permitting the recognition of various line errors by way of the pattern of the signals delivered at the outputs of the three comparators. As long as no line error is detected, the output signal of the first decoder is used for decoding. In case a line error is detected, the output signal either of the second or third comparator is used for decoding.
If the error recognition is carried out on the basis of the output signals delivered by the three comparators, the recognition of the presence of a line error is available only after assessment of the line potentials by the comparators. Only thereafter can switching over to the output of the comparator take place that is suitable for the line condition ascertained. Due to the fact that, for reaction of the comparators, the potentials on the lines must change first until the switching threshold value of the particular comparator is reached, which usually is in the range of the middle between the low and the high potential of the data transmission system, evaluation is possible only after passage of a considerable part of the respective pulse edges.
Problems also arise due to the fact that, for example due to different capacitive loads of the two lines, the ascending pulse edge occurring on one line in case of a bit change and the descending pulse edge occurring on the other line may be of different edge steepness and also of different edge duration. The moments of time at which the second and third comparators react on a bit change are different in such a case.
In order to obtain sensible evaluation results, it would have to be ascertained within a predetermined time slot whether, after the time the second or third comparator reports a pulse edge, also the other one of these two comparators signals a pulse edge. Without this measure, the error recognition circuit, at the time at which first only one of these two comparators reports a pulse edge while the other one of these two comparators does not yet report a pulse edge, erroneously would assume that the line whose comparator does not yet signal a pulse edge is inflicted with an error.
For realizing the foregoing solution that makes use of a time slot, a counter would need to be employed. What is disadvantageous with this approach is on the one hand that a very fast counter is necessary and on the other hand that a predetermined time slot is capable of ascertaining only deviations of the mutually associated pulse edges on the two lines up to an extent corresponding to the selected time slot.
The disclosed embodiments of the present invention make available an error recognition possibility that safely renders possible error recognition directly after the edge beginning and thus safely permits a reaction to a line error already ascertained at this early moment of time.
The signals on the two lines are each differentiated and the resulting differential signals together are summed up with a reference signal. From a comparison of the sum signal with the reference signal on the one hand and a comparison of each of the two differential signals with the sum signal on the other hand, conclusions can be made as to whether the lines are error-free, whether one of the two lines is open or has a short-circuit or whether the two lines are shorted to each other. By way of the resulting comparison result, it is then possible during decoding of the data pulses transmitted to switch over to the output of that one of the comparators that leads to a correct decoding result for the line condition ascertained. Due to the fact that the differential signals and thus the sum signal are already present as of the respective edge beginning, an error assessment and, resulting therefrom, switching over to the output of the suitable comparator thus is already possible at this early moment of time. Due to the fact that also with asymmetric line behavior, for example due to different capacitive loads of the two lines, the pulse edges start simultaneously on both lines, the time slot problem does not arise in the method according to the invention.
In one embodiment, a capacitor is employed in each of the two lines for differentiating, and three resistors are employed for summing. The latter are connected together in a summing point, with a first one of these resistors connecting the summing point to one line, a second one of these resistors connecting the summing point to the other line, and the third resistor connecting the summing point to a reference voltage source. Differential voltages can be used as differential signals, which leads to a sum voltage, and a reference voltage can be employed as reference signal.
In another embodiment, comparators are provided for the comparison of the thus resulting sum voltage to the reference voltage on the one hand and the comparison of the thus resulting differential voltages of the two lines to the sum voltage, with the output signals of these comparators being evaluated by means of a logic circuit and being converted into assessment signals. If the respective assessment signal leads to the result that no line error has been detected, the output signal of the comparator comparing the potentials of the two lines is used for decoding. In case an assessment signal in the form of an error signal occurs, decoding is carried out using the output signal of one of the two comparators which each evaluate the potential of only one of the two lines.
The outputs of the comparators evaluating the line potentials can be fed to a multiplexer which, depending on the type of the respective assessment signal, connects a data output at which the decoded data are taken off, through either to the output of the comparator comparing the potentials of the two lines with each other, to the output of the comparator evaluating the potential of the first line, or to the output of the comparator evaluating the potential of the second line.
In another embodiment of the invention, the result of the comparison in which the two differential signals are each compared with the sum signal, is utilized for decoding the data transmitted. In this case, the decoding result is available already at the respective edge beginning. Thus, very fast decoding can be achieved with this embodiment. The comparator comparing the potentials of the two lines with each other is not necessary in this embodiment. When a multiplexer is used, the decoding result obtained in this embodiment is fed to that signal input of the multiplexer which is provided for connection to the output of the comparator interconnecting the two lines (this comparator being not provided in this embodiment).